Traditional Chinese Practical Heart rate monitor (2): Circuit Design, Parts List & Workshop Prototype Guide

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Heart rate monitor(2)The heart rate monitor (II) is suitable for heart rate lower limit alarm, that is, it emits a sound signal when the heart rate is lower than a certain value, and the sound rhythm is the same as the heartbeat.The electrical schematic diagram of the heart rate monitor (II) is shown in Figure 23-1. The resistance value of resistor R3 determines the required lower limit of heart rate. The supply voltage is 3V and the quiescent current is 120mA.As can be seen from Figure 23-1, the working principle of part A is the same as the working principle of part A of the heart rate monitor (I) circuit (see Figure 22-2), and will not be repeated here.Part B is a sawtooth waveforming circuit; Part C is an analog thyristor gate circuit; Part D is an audio oscillator. The power supply charges capacitor C3 with constant current through VT5 and R3. When a pulse output from the integrated operational amplifier A1 arrives, VT1 is turned on, causing C3 to discharge. After this pulse passes, VT1 is cut off again and C3 is charged again. Repeat the above process from now on. As a result, a sawtooth wave voltage is formed at point b, and the waveform is shown in Figure 23-2. If the pulse interval is very small (that is, the heart rate is fast), the voltage on C3 cannot accumulate, and it will never reach the voltage value required to trigger the conduction of the next-level control gate, so the lower-level control gate will never open (cut off), and VT4 in part D will not get the forward bias current, so there will be no audio oscillation or sound. If the heart rate slows down and the voltage accumulated on C3 reaches the trigger voltage of the next stage (as shown in Figure 23-2), the control gate is triggered to flip (conduct), the final stage gets the bias current, and the oscillation circuit generates oscillation.Since the capacitor C3 discharges through the transistor VT1 (3DK5), its discharge time constant is much smaller than the width of the pulse, that is, it is discharged in a time much shorter than the pulse width, so the pulse width output by the operational amplifier A1 has no effect. alt="35.jpg (53802 bytes)">Figure 23-1In order to prevent errors when the power supply voltage decreases, the following measures have been taken: using the constant current characteristics of the field effect transistor to charge the capacitor C3, so that when the power supply voltage decreases, the periodic impact on the sawtooth wave is reduced. On the other hand, if the power supply voltage decreases, the pulse amplitude output at point a decreases, causing VT1 to exit the saturation zone early, the internal resistance of the tube increases, and the capacitor C3 cannot fully discharge, causing the residual voltage to increase, so the baseline of the sawtooth wave voltage increases accordingly. Originally, when the power supply voltage drops, the potential of the base point b decreases, but due to the small discharge of C3, the amplitude of the voltage at point b remains unchanged. In this way, the drop in power supply voltage is compensated. After testing, it can still work when the battery voltage is reduced to 2V. However, in order to ensure a certain test accuracy, the battery should be replaced when the battery voltage drops to 20%.Part C circuit is a PNP-NPN composite tube bistable trigger circuit. Normally, because the level of point b is low, VT3 (3DK5) is blocked, so VT2 has no bias current and the two tubes are cut off. This is a steady state. When the potential at point b increases, VT3 is turned on, and VT2 has a bias current and is also turned on. Once VT2 is turned on, it will provide a forward bias current to VT3 to protect itself. This is another steady state. The flipping of the two stable states is controlled by the potential of the base b of VT3. After the tube is turned off, it consumes no power and very little electricity. When the sawtooth wave voltage amplitude reaches the trigger threshold voltage as shown in Figure 23-2, the circuit flips, VT2 and VT3 are turned on, thus providing a bias current for the next stage, the final stage oscillates, and the piezoelectric ceramic piece makes sound. When VT1 is controlled to be turned on by the output pulse of operational amplifier A1, point b is equivalent to grounding, forcing the bistable circuit to flip, and both tubes are cut off at the same time until the next sawtooth wave is triggered.Part D circuit is a self-excited intermittent oscillator with a frequency of about 2000Hz. Its advantage is high efficiency. When the slow heart rate increases the potential of point b in Figure 23-1, causing VT2 and VT3 to enter the conduction saturation state, the base of VT4 obtains a bias, the intermittent oscillator starts to work, and the piezoelectric ceramic chip emits an audio signal sound. In this way, as long as the ECG pulse frequency is lower than a certain value, the potential at point b can rise enough to cause VT2 and VT3 to enter the conduction saturation state, and the piezoelectric ceramic piece will sound. As many times as the heart rate per second, the ceramic piece will also sound the same number of times per second (see Figure 23-2). Obviously, the beat frequency of the sound produced by the piezoelectric ceramic piece at this time is the same as the heart rate of the person being tested. If the person's heart rate is not very low, the potential at point b is not enough to conduct VT2 and VT3, and the piezoelectric ceramic piece will not make any sound. …

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